In recent years, a synchronous rectification type DC-DC converter is often used as a switching type DC-DC converter configured to supply power supply voltage to various types of electronic devices. In a synchronous rectification type DC-DC converter, in which an MOS-transistor switch element is used as a rectification element to reduce a rectification loss. In such a DC-DC converter, a main transistor and a synchronization transistor are controlled so as to be alternately activated and inactivated to maintain an output voltage at a target voltage. That is, the main transistor is activated to supply energy from an input to an output and then inactivated to discharge the energy accumulated in a choke coil. In this state, in synchronization with a timing at which the energy accumulated in the choke coil is discharged to a load, the synchronization transistor is activated. Then, the output voltage is maintained at the target voltage by controlling a duty ratio of a pulse signal that drives the main transistor based on the output voltage or current.
In such a DC-DC converter, when the main transistor is inactivated and the load is small, current flows from the load to ground through the synchronization transistor. This results in an energy loss. Thus, the conversion efficiency of the DC-DC converter is reduced when the load is small.
To solve this problem, U.S. Patent Application Publication Nos. 2008/0246455 and 2008/0298106 describe a DC-DC converter configured to inactivate the synchronization transistor when a reverse flow of a coil current in a choke coil is detected. Further, International Patent Publication No. 2006/123738 describes a DC-DC converter that obtains a period from when the synchronization transistor is inactivated to when the voltage at a node between the main transistor and the synchronization transistor rises to a given threshold value. Based on the period, the DC-DC converter controls an inactivation period of the synchronization transistor in subsequent cycles.
However, process variations or the like may adversely affect the accuracy for detecting reverse flows. This decreases the conversion efficiency when the load is small.
Further, the coil current may flow reversely even when the inactivation period of the synchronization transistor is controlled based on the potential accumulated in a capacitor in the period from when the synchronization transistor is inactivated to when the voltage at the node between the main transistor and the synchronization transistor rises to the given threshold value. In this case, when charge is drawn out from the capacitor by applying a one-shot pulse in each cycle, the timing at which the synchronization transistor shifts to an inactivated state varies. In such a DC-DC converter, the activated period of the synchronization transistor is stabilized when the charging and discharging of the capacitor are balanced with each other. Accordingly, the timing at which the synchronization transistor is inactivated is always offset at a timing when the coil current is reduced to zero during a period in which the charged amount of the capacitor is balanced with the amount of charge drawn out by the one-shot pulse. Therefore, in such a DC-DC converter, the existence of an offset period lowers the reverse flow detection accuracy. This may reduce the conversion efficiency when the load is small.